This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-259151, Aug. 29, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor storage device including a main memory cell array and a redundancy memory cell array and a setting method thereof, and particularly to a technique for effectively using the redundancy memory cell array.
2. Description of the Related Art
A semiconductor storage device, such as a semiconductor storage device of a serial access type, is provided with a redundancy memory cell array as well as a main memory cell array, to improve the productivity. The main memory cell array and the redundancy memory cell array include a plurality of memory cells to perform writing, reading, and erasing of data. Where there is a defective memory cell in the main memory cell array, the defective memory cell is replaced with a memory cell in the redundancy memory cell array.
FIG. 9 is a block diagram showing conventional partitioning of memory cell arrays and memory access routes. The memory cell arrays include a main memory cell array 1 and a redundancy memory cell array 2. Where a defective memory cell or a defective wiring line occurs in the main memory cell array 1, a memory cell in the redundancy memory cell array 2, which is an extra memory cell array prepared in advance, is set to be accessed, in place of the defective.
In FIG. 9, the vertical direction is the row direction Dr, and the horizontal direction is the column direction Dc. The number of memory cells in the row direction Dr and the column direction Dc is preset in light of the memory capacity. The columns of the main memory cell array 1 and the redundancy memory cell array 2 are respectively connected to selection signal lines 3. Those of the selection signal lines 3, which are connected to the columns of the main memory cell array 1, are connected to the main memory selection circuit 29. Those of the selection signal lines 3, which are connected to the columns of the redundancy memory cell array 2, are connected to the redundancy memory selection circuit 30. An address signal line 31 is connected to the main memory selection circuit 29 and the redundancy memory selection circuit 30.
A column isolation fuse group 27 is connected to the main memory selection circuit 29. A redundancy access fuse group 28 is connected to the redundancy memory selection circuit 30. Where there is a defective memory cell in the main memory cell array 1, a fuse corresponding thereto in the column isolation fuse group 27 is cut to avoid access to the defective memory cell. In addition, a fuse corresponding to a memory cell to be accessed is cut in the redundancy access fuse group 28. At this time a plurality of fuses are cut so that one redundancy column is automatically selected when the address of a defective column is selected. The combination of the cut fuses designates the address of the defective column to be replaced.
FIG. 10 is a block diagram showing the memory cell arrays partitioned and prepared by cutting some fuses. The redundancy memory cell array 2 is used only for the purpose of providing memory cells to be accessed in place of defective memory cells in the main memory cell array 1. In FIG. 10, memory cell areas that can be accessed by main memory access commands are limited to normal memory cell areas MG1 and MG2 in the main memory cell array 1, and a replacing memory cell area RG1 in the redundancy memory cell array 2, which replaces a defective memory cell area MF1 in the main memory cell array 1.
Access to the redundancy memory cell array 2 requires a redundancy memory access command. In other words, in order to access an area RG2 in the redundancy memory cell array 2 shown in FIG. 10, other than the replacing memory cell area RG1, a special command has to be used.
When trimming a semiconductor storage device, it is necessary to test whether programming, erasing, and reading are properly performed, so as to determine defective memory cells. Specifically, a writing/reading operation and an erasing/reading operation are performed on the main memory cell array 1. If a defective memory cell, from which correct data is not read, is confirmed in the main memory cell array 1, a memory cell in the redundancy memory cell array 2 is assigned to a replacing memory cell candidate corresponding to the defective memory cell. Then, a writing/reading operation and an erasing/reading operation are performed on the replacing memory cell candidate. If correct data is read from this candidate, it is determined to use the candidate as the replacing memory cell.
If the correct data is not read from this candidate, another memory cell in the redundancy memory cell array 2 is reassigned to a replacing memory cell candidate. Then, as described above, a writing/reading operation and an erasing/reading operation are performed also on the reassigned candidate. If correct data is read from this reassigned candidate, it is determined to use the candidate as the replacing memory cell. If the correct data is not read from this reassigned candidate, another memory cell in the redundancy memory cell array 2 is further reassigned to a replacing memory cell candidate. This reassignment is repeatedly performed until a replacing candidate, from which the correct data is read, is found.
In the case of using main memory access commands and redundancy memory access commands, a defective memory cell is determined as follows. In this case, only the main memory cell array is accessible by inputting main memory access commands, while only the redundancy memory cell array is accessible by inputting redundancy memory access commands.
Specifically, a writing/reading operation and an erasing/reading operation are performed on the main memory cell array 1. If a defective area, from which correct data is not read, is confirmed in the main memory cell array 1, a specific area in the redundancy memory cell array 2 is assigned. Then, a writing/reading operation and an erasing/reading operation are performed on this specific area. If correct data is read from this specific area, it is determined to use the specific area as the replacing area. If correct data is not read from this specific area, a search for another area, from which correct data is read, is performed to use it as the replacing area.
Using either one of the two methods described above, a defective memory cell in the main memory cell array 1 is replaced with a normal memory cell in the redundancy memory cell array 2.
According to a first aspect of the present invention, there is provided a semiconductor storage device comprising:
a main memory cell array including a plurality of memory cells;
a redundancy memory cell array including a plurality of memory cells, which are usable to replace a defective memory cell in the main memory cell array, the redundancy memory cell array being set to selectively have a replacing area replacing a defective memory cell in the main memory cell array, and a non-replacing area other than the replacing area;
a memory selection circuit configured to select and drive memory cells in the main memory cell array and the redundancy memory cell array;
a control section configured to control the memory selection circuit, the control section being set to assign main memory addresses to memory cells in the non-replacing area, and use these memory cells as an expansion area of the main memory cell array.
According to a second aspect of the present invention, there is provided a semiconductor storage device comprising:
a main memory cell array including a plurality of memory cells;
a redundancy memory cell array including a plurality of memory cells, which are usable to replace a defective memory cell in the main memory cell array;
a memory selection circuit configured to select and drive memory cells in the main memory cell array and the redundancy memory cell array, the memory selection circuit including a replacing circuit portion configured to replace a defective memory cell in the main memory cell array with a memory cell in the redundancy memory cell array, and the redundancy memory cell array being set by the replacing circuit portion to selectively have a replacing area replacing a defective memory cell in the main memory cell array, and a non-replacing area other than the replacing area;
an address increment circuit configured to supply the memory selection circuit with an address signal having address numbers gradually increased from a main memory address, so as to access memory cells in the non-replacing area, in succession to memory cells in the main memory cell array; and
an end address control circuit configured to generate an end signal indicating that a selected specific address in the non-replacing area is an end address, wherein the address increment circuit stops operating upon the end signal being present.
According to a third aspect of the present invention, there is provided a method of setting a semiconductor storage device, comprising:
setting a redundancy memory cell array to selectively have a replacing area replacing a defective memory cell in a main memory cell array, and a non-replacing area other than the replacing area; and
setting a control section to assign main memory addresses to memory cells in the non-replacing area, and use these memory cells as an expansion area of the main memory cell array, wherein the control section controls the memory selection circuit configured to select and drive memory cells in the main memory cell array and the redundancy memory cell array.